2017-05-10 12:00:41 +02:00
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using System;
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using System.Collections.Generic;
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using System.Text.RegularExpressions;
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namespace PIC_Simulator.PIC
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{
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class PICBefehl
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{
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public string befehl;
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public uint parameter_d;
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public uint parameter_f;
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public uint parameter_x;
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public uint parameter_k;
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public uint parameter_b;
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2017-05-10 16:30:58 +02:00
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public int labelnummer;
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2017-05-10 12:00:41 +02:00
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public int zeilennummer;
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}
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class PICProgramm
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{
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public const uint ADDR_INDF = 0x00;
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public const uint ADDR_TMR0 = 0x01;
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public const uint ADDR_PCL = 0x02;
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public const uint ADDR_STATUS = 0x03;
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public const uint ADDR_FSR = 0x04;
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public const uint ADDR_PORT_A = 0x05;
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public const uint ADDR_PORT_B = 0x06;
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public const uint ADDR_UNIMPL_A = 0x07;
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public const uint ADDR_PCLATH = 0x0A;
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public const uint ADDR_INTCON = 0x0B;
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public const uint ADDR_OPTION = 0x81;
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public const uint ADDR_TRIS_A = 0x85;
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public const uint ADDR_TRIS_B = 0x86;
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public const uint ADDR_UNIMPL_B = 0x87;
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public const uint ADDR_EECON1 = 0x88;
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public const uint ADDR_EECON2 = 0x89;
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public const uint STATUS_BIT_IRP = 7; // Unused in PIC16C84
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public const uint STATUS_BIT_RP1 = 6; // Register Bank Selection Bit [1] (Unused in PIC16C84)
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public const uint STATUS_BIT_RP0 = 5; // Register Bank Selection Bit [0]
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public const uint STATUS_BIT_TO = 4; // Time Out Bit
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public const uint STATUS_BIT_PD = 3; // Power Down Bit
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public const uint STATUS_BIT_Z = 2; // Zero Bit
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public const uint STATUS_BIT_DC = 1; // Digit Carry Bit
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public const uint STATUS_BIT_C = 0; // Carry Bit
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public const uint OPTION_BIT_RBPU = 7; // PORT-B Pull-Up Enable Bit
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public const uint OPTION_BIT_INTEDG = 6; // Interrupt Edge Select Bit
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public const uint OPTION_BIT_T0CS = 5; // TMR0 Clock Source Select Bit
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public const uint OPTION_BIT_T0SE = 4; // TMR0 Source Edge Select Bit
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public const uint OPTION_BIT_PSA = 3; // Prescaler Alignment Bit
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public const uint OPTION_BIT_PS2 = 2; // Prescaler Rate Select Bit [2]
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public const uint OPTION_BIT_PS1 = 1; // Prescaler Rate Select Bit [1]
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public const uint OPTION_BIT_PS0 = 0; // Prescaler Rate Select Bit [0]
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public const uint INTCON_BIT_GIE = 7; // Global Interrupt Enable Bit
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public const uint INTCON_BIT_EEIE = 6; // EE Write Complete Interrupt Enable Bit
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public const uint INTCON_BIT_T0IE = 5; // TMR0 Overflow Interrupt Enable Bit
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public const uint INTCON_BIT_INTE = 4; // RB0/INT Interrupt Bit
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public const uint INTCON_BIT_RBIE = 3; // RB Port Change Interrupt Enable Bit
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public const uint INTCON_BIT_T0IF = 2; // TMR0 Overflow Interrupt Flag Bit
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public const uint INTCON_BIT_INTF = 1; // RB0/INT Interrupt Flag Bit
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public const uint INTCON_BIT_RBIF = 0; // RB Port Change Interrupt Flag Bit
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public const string ADDWF = "000111dfffffff";
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public const string ANDWF = "000101dfffffff";
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public const string CLRF = "0000011fffffff";
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public const string CLRW = "0000010xxxxxxx";
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public const string COMF = "001001dfffffff";
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public const string DECF = "000011dfffffff";
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public const string DECFSZ = "001011dfffffff";
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public const string INCF = "001010dfffffff";
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public const string INCFSZ = "001111dfffffff";
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public const string IORWF = "000100dfffffff";
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public const string MOVF = "001000dfffffff";
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public const string MOVWF = "0000001fffffff";
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public const string NOP = "0000000xx00000";
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public const string RLF = "001101dfffffff";
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public const string RRF = "001100dfffffff";
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public const string SUBWF = "000010dfffffff";
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public const string SWAPF = "001110dfffffff";
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public const string XORWF = "000110dfffffff";
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public const string BCF = "0100bbbfffffff";
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public const string BSF = "0101bbbfffffff";
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public const string BTFSC = "0110bbbfffffff";
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public const string BTFSS = "0111bbbfffffff";
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public const string ADDLW = "11111xkkkkkkkk";
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public const string ANDLW = "111001kkkkkkkk";
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public const string CALL = "100kkkkkkkkkkk";
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public const string CLRWDT = "00000001100100";
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public const string GOTO = "101kkkkkkkkkkk";
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public const string IORLW = "111000kkkkkkkk";
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public const string MOVLW = "1100xxkkkkkkkk";
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public const string RETFIE = "00000000001001";
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public const string RETLW = "1101xxkkkkkkkk";
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public const string RETURN = "00000000001000";
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public const string SLEEP = "00000001100011";
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public const string SUBLW = "11110xkkkkkkkk";
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public const string XORLW = "111010kkkkkkkk";
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public string[] ALL_COMMANDS = {ADDWF, ANDWF, CLRF, CLRW, COMF, DECF, DECFSZ, INCF, INCFSZ, IORWF, MOVF, MOVWF, NOP, RLF, RRF, SUBWF, SWAPF, XORWF, BCF, BSF, BTFSC, BTFSS, ADDLW, ANDLW, CALL, CLRWDT, GOTO, IORLW, MOVLW, RETFIE, RETLW, RETURN, SLEEP, SUBLW, XORLW };
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public List<PICBefehl> befehle;
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public int PCCounter = 0; // -> nächster befehl
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2017-05-10 16:30:58 +02:00
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public int Stepcount = 0;
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2017-05-10 12:00:41 +02:00
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public uint Register_W = 0;
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public uint[] Register = new uint[0x100];
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2017-05-10 19:20:15 +02:00
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public Stack<uint> Stack = new Stack<uint>();
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2017-05-11 11:13:09 +02:00
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public bool IsSleeping = false;
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2017-05-10 12:00:41 +02:00
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2017-05-11 11:58:44 +02:00
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public List<int> Breakpoints = new List<int>();
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public int TaktgeberFrequenz = 100000;
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public int TaktgeberZahler = 100000;
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public bool TaktgeberAktiviert = false;
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public uint TaktgeberAdresse = 0;
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public uint TaktgeberBitnummer = 0;
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2017-05-11 10:08:48 +02:00
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2017-05-10 12:00:41 +02:00
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public PICProgramm()
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{
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2017-05-11 11:43:11 +02:00
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// Anfangswerte
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SetRegisterOhneBank(ADDR_PCL, 0x00);
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SetRegisterOhneBank(ADDR_STATUS, 0x18);
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SetRegisterOhneBank(ADDR_PCLATH, 0x00);
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SetRegisterOhneBank(ADDR_INTCON, 0x00);
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SetRegisterOhneBank(ADDR_OPTION, 0xFF);
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SetRegisterOhneBank(ADDR_TRIS_A, 0x1F);
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SetRegisterOhneBank(ADDR_TRIS_B, 0xFF);
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SetRegisterOhneBank(ADDR_EECON1, 0x00);
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SetRegisterOhneBank(ADDR_EECON2, 0x00);
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2017-05-10 12:00:41 +02:00
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}
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public void Laden(string code)
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{
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befehle = new List<PICBefehl>();
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2017-05-10 16:30:58 +02:00
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int zn = -1;
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2017-05-10 12:00:41 +02:00
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foreach (var zeile in Regex.Split(code, @"\r?\n"))
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{
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zn++;
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if (zeile.StartsWith(" ")) continue;
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if (zeile.Length < 10) continue;
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befehle.Add(FindeBefehl(zeile, zn));
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}
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}
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private PICBefehl FindeBefehl(string zeile, int zeilennummer)
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{
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foreach (var cmd in ALL_COMMANDS)
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{
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string bin = hex2binary(zeile.Substring(5, 4));
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uint p_d = 0;
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uint p_f = 0;
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uint p_x = 0;
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uint p_k = 0;
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uint p_b = 0;
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bool ok = true;
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for (int i = 0; i < 14; i++)
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{
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if (cmd[i] == '0' && bin[i] == '0') continue;
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if (cmd[i] == '1' && bin[i] == '1') continue;
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if (cmd[i] == 'd' && bin[i] == '0') { p_d <<= 1; p_d |= 0; continue; }
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if (cmd[i] == 'd' && bin[i] == '1') { p_d <<= 1; p_d |= 1; continue; }
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if (cmd[i] == 'f' && bin[i] == '0') { p_f <<= 1; p_f |= 0; continue; }
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if (cmd[i] == 'f' && bin[i] == '1') { p_f <<= 1; p_f |= 1; continue; }
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if (cmd[i] == 'x' && bin[i] == '0') { p_x <<= 1; p_x |= 0; continue; }
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if (cmd[i] == 'x' && bin[i] == '1') { p_x <<= 1; p_x |= 1; continue; }
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if (cmd[i] == 'k' && bin[i] == '0') { p_k <<= 1; p_k |= 0; continue; }
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if (cmd[i] == 'k' && bin[i] == '1') { p_k <<= 1; p_k |= 1; continue; }
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if (cmd[i] == 'b' && bin[i] == '0') { p_b <<= 1; p_b |= 0; continue; }
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if (cmd[i] == 'b' && bin[i] == '1') { p_b <<= 1; p_b |= 1; continue; }
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if (cmd[i] == '0' && bin[i] == '1') { ok = false; break; }
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if (cmd[i] == '1' && bin[i] == '0') { ok = false; continue; }
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throw new Exception("Falscher wert in cmd");
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}
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if (ok)
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{
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PICBefehl b = new PICBefehl();
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b.befehl = cmd;
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b.parameter_d = p_d;
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b.parameter_f = p_f;
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b.parameter_k = p_k;
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b.parameter_x = p_x;
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b.parameter_b = p_b;
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b.zeilennummer = zeilennummer;
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2017-05-10 16:30:58 +02:00
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b.labelnummer = Convert.ToInt32(zeile.Substring(0, 4), 16);
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2017-05-10 12:00:41 +02:00
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return b;
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}
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}
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throw new Exception("konnte befehl nicht finden: " + zeile);
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}
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private string hex2binary(string hexvalue)
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{
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string binaryval = "";
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binaryval = Convert.ToString(Convert.ToInt32(hexvalue, 16), 2).PadLeft(14, '0');
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return binaryval;
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}
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2017-05-11 11:58:44 +02:00
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public bool Step(int frequenz)
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2017-05-10 12:00:41 +02:00
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{
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if (PCCounter >= befehle.Count) return true;
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PICBefehl aktueller_befehl = befehle[PCCounter];
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2017-05-11 11:58:44 +02:00
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if (TaktgeberAktiviert)
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{
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TaktgeberZahler += frequenz;
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if (TaktgeberZahler > TaktgeberFrequenz)
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{
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TaktgeberZahler = 0;
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SetRegisterOhneBank(TaktgeberAdresse, TaktgeberBitnummer, !GetRegisterOhneBank(TaktgeberAdresse, TaktgeberBitnummer));
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}
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}
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2017-05-11 11:13:09 +02:00
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if (IsSleeping) return false;
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2017-05-10 12:00:41 +02:00
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if (aktueller_befehl.befehl == ADDWF)
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{
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2017-05-10 19:20:15 +02:00
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// Add the contents of the W register with
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// register 'f'.If 'd' is 0 the result is stored
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// in the W register.If 'd' is 1 the result is
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// stored back in register 'f'.
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2017-05-10 12:00:41 +02:00
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uint a = GetRegister(aktueller_befehl.parameter_f);
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uint b = Register_W;
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uint Result = a + b;
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bool dc = AdditionDigitCarry(a, b);
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SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, (Result % 0x100) == 0);
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SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_DC, dc);
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SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, Result > 0xFF);
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Result %= 0x100;
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if (aktueller_befehl.parameter_d != 0)
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SetRegister(aktueller_befehl.parameter_f, Result);
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else
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Register_W = Result;
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}
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else if (aktueller_befehl.befehl == ANDWF)
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{
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2017-05-10 19:20:15 +02:00
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// AND the W register with register 'f'.If 'd'
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// is 0 the result is stored in the W regis -
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// ter.If 'd' is 1 the result is stored back in
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// register 'f'
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2017-05-10 12:00:41 +02:00
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uint Result = Register_W & GetRegister(aktueller_befehl.parameter_f);
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SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
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if (aktueller_befehl.parameter_d != 0)
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SetRegister(aktueller_befehl.parameter_f, Result);
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else
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Register_W = Result;
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}
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else if (aktueller_befehl.befehl == CLRF)
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{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are cleared
|
|
|
|
|
// and the Z bit is set.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, 0x00);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, true);
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == CLRW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// W register is cleared.Zero bit (Z) is
|
|
|
|
|
// set.
|
|
|
|
|
|
|
|
|
|
Register_W = 0;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, true);
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == COMF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are comple-
|
|
|
|
|
// mented.If 'd' is 0 the result is stored in
|
|
|
|
|
// W.If 'd' is 1 the result is stored back in
|
|
|
|
|
// register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = ~GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == DECF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Decrement register 'f'.If 'd' is 0 the
|
|
|
|
|
// result is stored in the W register.If 'd' is
|
|
|
|
|
// 1 the result is stored back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
if (Result == 0)
|
|
|
|
|
Result = 0xFF;
|
|
|
|
|
else
|
|
|
|
|
Result -= 1;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == DECFSZ)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are decre-
|
|
|
|
|
// mented.If 'd' is 0 the result is placed in the
|
|
|
|
|
// W register.If 'd' is 1 the result is placed
|
|
|
|
|
// back in register 'f'.
|
|
|
|
|
// If the result is 1, the next instruction, is
|
|
|
|
|
// executed.If the result is 0, then a NOP is
|
|
|
|
|
// executed instead making it a 2T CY instruc -
|
|
|
|
|
// tion.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
bool Cond = GetRegister(aktueller_befehl.parameter_f) == 1;
|
|
|
|
|
|
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
if (Result == 0)
|
|
|
|
|
Result = 0xFF;
|
|
|
|
|
else
|
|
|
|
|
Result -= 1;
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
|
|
|
|
|
if (Cond)
|
|
|
|
|
{
|
|
|
|
|
PCCounter++; // skip next
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == INCF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are incre-
|
|
|
|
|
// mented.If 'd' is 0 the result is placed in
|
|
|
|
|
// the W register.If 'd' is 1 the result is
|
|
|
|
|
// placed back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
Result += 1;
|
|
|
|
|
|
|
|
|
|
Result %= 0x100;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == INCFSZ)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are incre-
|
|
|
|
|
// mented.If 'd' is 0 the result is placed in
|
|
|
|
|
// the W register.If 'd' is 1 the result is
|
|
|
|
|
// placed back in register 'f'.
|
|
|
|
|
// If the result is 1, the next instruction is
|
|
|
|
|
// executed.If the result is 0, a NOP is exe -
|
|
|
|
|
// cuted instead making it a 2T CY instruc -
|
|
|
|
|
// tion
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
bool Cond = GetRegister(aktueller_befehl.parameter_f) == 0xFF;
|
|
|
|
|
|
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
Result += 1;
|
|
|
|
|
|
|
|
|
|
Result %= 0x100;
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
|
|
|
|
|
if (Cond)
|
|
|
|
|
{
|
|
|
|
|
PCCounter++; // skip next
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == IORWF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Inclusive OR the W register with regis -
|
|
|
|
|
// ter 'f'.If 'd' is 0 the result is placed in the
|
|
|
|
|
// W register.If 'd' is 1 the result is placed
|
|
|
|
|
// back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = Register_W | GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == MOVF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register f is moved to a
|
|
|
|
|
// destination dependant upon the status
|
|
|
|
|
// of d. If d = 0, destination is W register. If
|
|
|
|
|
// d = 1, the destination is file register f
|
|
|
|
|
// itself.d = 1 is useful to test a file regis-
|
|
|
|
|
// ter since status flag Z is affected.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == MOVWF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Move data from W register to register
|
|
|
|
|
// 'f'
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Register_W);
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == NOP)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
//No operation.
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == RLF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are rotated
|
|
|
|
|
// one bit to the left through the Carry
|
|
|
|
|
// Flag.If 'd' is 0 the result is placed in the
|
|
|
|
|
// W register.If 'd' is 1 the result is stored
|
|
|
|
|
// back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
uint Carry_Old = GetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C) ? 1u : 0u;
|
|
|
|
|
uint Carry_New = (Result & 0x80) >> 7;
|
|
|
|
|
|
|
|
|
|
Result = Result << 1;
|
|
|
|
|
Result &= 0xFF;
|
|
|
|
|
|
|
|
|
|
Result |= Carry_Old;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, Carry_New != 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == RRF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of register 'f' are rotated
|
|
|
|
|
// one bit to the right through the Carry
|
|
|
|
|
// Flag.If 'd' is 0 the result is placed in the
|
|
|
|
|
// W register.If 'd' is 1 the result is placed
|
|
|
|
|
// back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
uint Carry_Old = GetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C) ? 0x80u : 0x00u;
|
|
|
|
|
uint Carry_New = Result & 0x01;
|
|
|
|
|
|
|
|
|
|
Result = Result >> 1;
|
|
|
|
|
Result &= 0xFF;
|
|
|
|
|
|
|
|
|
|
Result |= Carry_Old;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, Carry_New != 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == SUBWF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Subtract(2’s complement method) W reg-
|
|
|
|
|
// ister from register 'f'.If 'd' is 0 the result is
|
|
|
|
|
// stored in the W register.If 'd' is 1 the
|
|
|
|
|
// result is stored back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint a = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
uint b = Register_W;
|
|
|
|
|
|
|
|
|
|
bool carry;
|
|
|
|
|
|
|
|
|
|
bool dc = SubtractionDigitCarry(a, b);
|
|
|
|
|
|
|
|
|
|
if (carry = a < b)
|
|
|
|
|
{
|
|
|
|
|
a += 0x100;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint Result = a - b;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, (Result % 0x100) == 0);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_DC, dc);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, !carry);
|
|
|
|
|
|
|
|
|
|
Result %= 0x100;
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == SWAPF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The upper and lower nibbles of register
|
|
|
|
|
// 'f' are exchanged. If 'd' is 0 the result is
|
|
|
|
|
// placed in W register. If 'd' is 1 the result
|
|
|
|
|
// is placed in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
uint Low = Result & 0x0F;
|
|
|
|
|
uint High = Result & 0xF0;
|
|
|
|
|
|
|
|
|
|
Result = (Low << 4) | (High >> 4);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == XORWF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Exclusive OR the contents of the W
|
|
|
|
|
// register with register 'f'.If 'd' is 0 the
|
|
|
|
|
// result is stored in the W register.If 'd' is
|
|
|
|
|
// 1 the result is stored back in register 'f'.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = Register_W ^ GetRegister(aktueller_befehl.parameter_f);
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
if (aktueller_befehl.parameter_d != 0)
|
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, Result);
|
|
|
|
|
else
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == BCF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Bit 'b' in register 'f' is cleared
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, aktueller_befehl.parameter_b, false);
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == BSF)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Bit 'b' in register 'f' is set.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
SetRegister(aktueller_befehl.parameter_f, aktueller_befehl.parameter_b, true);
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == BTFSC)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// If bit 'b' in register 'f' is '1' then the next
|
|
|
|
|
// instruction is executed.
|
|
|
|
|
// If bit 'b', in register 'f', is '0' then the next
|
|
|
|
|
// instruction is discarded, and a NOP is
|
|
|
|
|
// executed instead, making this a 2T CY
|
|
|
|
|
// instruction
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
if (!GetBit(GetRegister(aktueller_befehl.parameter_f), aktueller_befehl.parameter_b))
|
|
|
|
|
{
|
|
|
|
|
PCCounter++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == BTFSS)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// If bit 'b' in register 'f' is '0' then the next
|
|
|
|
|
// instruction is executed.
|
|
|
|
|
// If bit 'b' is '1', then the next instruction is
|
|
|
|
|
// discarded and a NOP is executed
|
|
|
|
|
// instead, making this a 2T CY instruction.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
if (GetBit(GetRegister(aktueller_befehl.parameter_f), aktueller_befehl.parameter_b))
|
|
|
|
|
{
|
|
|
|
|
PCCounter++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == ADDLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of the W register are
|
|
|
|
|
// added to the eight bit literal 'k' and the
|
|
|
|
|
// result is placed in the W register
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint a = Register_W;
|
|
|
|
|
uint b = aktueller_befehl.parameter_k;
|
|
|
|
|
|
|
|
|
|
uint Result = a + b;
|
|
|
|
|
bool dc = AdditionDigitCarry(a, b);
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, (Result % 0x100) == 0);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_DC, dc);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, Result > 0xFF);
|
|
|
|
|
|
|
|
|
|
Result %= 0x100;
|
|
|
|
|
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == ANDLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of W register are
|
|
|
|
|
// AND’ed with the eight bit literal 'k'.The
|
|
|
|
|
// result is placed in the W register
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = Register_W & aktueller_befehl.parameter_k;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == CALL)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Call Subroutine. First, return address
|
|
|
|
|
// (PC + 1) is pushed onto the stack. The
|
|
|
|
|
// eleven bit immediate address is loaded
|
|
|
|
|
// into PC bits<10:0 >.The upper bits of
|
|
|
|
|
// the PC are loaded from PCLATH.CALL
|
|
|
|
|
// is a two cycle instruction.
|
|
|
|
|
|
|
|
|
|
Stack.Push((uint) PCCounter);
|
|
|
|
|
PCCounter = (int) (aktueller_befehl.parameter_k - 1);
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == CLRWDT)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// CLRWDT instruction resets the Watch -
|
|
|
|
|
// dog Timer.It also resets the prescaler
|
|
|
|
|
// of the WDT. Status bits TO and PD are
|
|
|
|
|
// set.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
//TODO
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == GOTO)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// GOTO is an unconditional branch.The
|
|
|
|
|
// eleven bit immediate value is loaded
|
|
|
|
|
// into PC bits<10:0>.The upper bits of
|
|
|
|
|
// PC are loaded from PCLATH<4:3>.
|
|
|
|
|
// GOTO is a two cycle instruction.
|
|
|
|
|
|
2017-05-10 16:30:58 +02:00
|
|
|
|
PCCounter = befehle.FindIndex(b => b.labelnummer == aktueller_befehl.parameter_k) - 1;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == IORLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of the W register is
|
|
|
|
|
// OR’ed with the eight bit literal 'k'.The
|
|
|
|
|
// result is placed in the W register
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = Register_W | aktueller_befehl.parameter_k;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == MOVLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The eight bit literal 'k' is loaded into W
|
|
|
|
|
// register.The don’t cares will assemble
|
|
|
|
|
// as 0’s.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
Register_W = aktueller_befehl.parameter_k;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == RETFIE)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Return from Interrupt.Stack is POPed
|
|
|
|
|
// and Top of Stack(TOS) is loaded in the
|
|
|
|
|
// PC.Interrupts are enabled by setting
|
|
|
|
|
// Global Interrupt Enable bit, GIE
|
|
|
|
|
// (INTCON < 7 >).This is a two cycle
|
|
|
|
|
// instruction.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
//TODO
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == RETLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The W register is loaded with the eight
|
|
|
|
|
// bit literal 'k'.The program counter is
|
|
|
|
|
// loaded from the top of the stack(the
|
|
|
|
|
// return address). This is a two cycle
|
|
|
|
|
// instruction.
|
|
|
|
|
Register_W = aktueller_befehl.parameter_k;
|
|
|
|
|
PCCounter = (int) Stack.Pop();
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == RETURN)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// Return from subroutine. The stack is
|
|
|
|
|
// POPed and the top of the stack(TOS)
|
|
|
|
|
// is loaded into the program counter.This
|
|
|
|
|
// is a two cycle instruction.
|
|
|
|
|
PCCounter = (int)Stack.Pop();
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == SLEEP)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The power-down status bit, PD is
|
|
|
|
|
// cleared.Time -out status bit, TO is
|
|
|
|
|
// set.Watchdog Timer and its prescaler
|
|
|
|
|
// are cleared.
|
|
|
|
|
// The processor is put into SLEEP
|
|
|
|
|
// mode with the oscillator stopped. See
|
|
|
|
|
// Section 14.8 for more details.
|
|
|
|
|
|
2017-05-11 11:13:09 +02:00
|
|
|
|
if (GetRegisterOhneBank(ADDR_OPTION, OPTION_BIT_PSA))
|
|
|
|
|
{
|
|
|
|
|
SetRegisterOhneBank(ADDR_OPTION, OPTION_BIT_PS0, false);
|
|
|
|
|
SetRegisterOhneBank(ADDR_OPTION, OPTION_BIT_PS1, false);
|
|
|
|
|
SetRegisterOhneBank(ADDR_OPTION, OPTION_BIT_PS2, false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_TO, true);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_PD, false);
|
|
|
|
|
|
|
|
|
|
IsSleeping = true;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == SUBLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The W register is subtracted (2’s comple-
|
|
|
|
|
// ment method) from the eight bit literal 'k'.
|
|
|
|
|
// The result is placed in the W register.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint a = aktueller_befehl.parameter_k;
|
|
|
|
|
uint b = Register_W;
|
|
|
|
|
|
|
|
|
|
bool carry;
|
|
|
|
|
|
|
|
|
|
bool dc = SubtractionDigitCarry(a, b);
|
|
|
|
|
|
|
|
|
|
if (carry = a < b)
|
|
|
|
|
{
|
|
|
|
|
a += 0x100;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint Result = a - b;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, (Result % 0x100) == 0);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_DC, dc);
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_C, !carry);
|
|
|
|
|
|
|
|
|
|
Result %= 0x100;
|
|
|
|
|
|
|
|
|
|
Register_W = Result;
|
|
|
|
|
}
|
|
|
|
|
else if (aktueller_befehl.befehl == XORLW)
|
|
|
|
|
{
|
2017-05-10 19:20:15 +02:00
|
|
|
|
// The contents of the W register are
|
|
|
|
|
// XOR’ed with the eight bit literal 'k'.
|
|
|
|
|
// The result is placed in the W regis -
|
|
|
|
|
// ter.
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
uint Result = Register_W ^ aktueller_befehl.parameter_k;
|
|
|
|
|
|
|
|
|
|
SetRegisterOhneBank(ADDR_STATUS, STATUS_BIT_Z, Result == 0);
|
|
|
|
|
|
|
|
|
|
Register_W = Result; ;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-10 16:30:58 +02:00
|
|
|
|
PCCounter++;
|
|
|
|
|
Stepcount++;
|
|
|
|
|
|
|
|
|
|
return PCCounter >= befehle.Count;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
public void SetRegisterOhneBank(uint index, uint wert)
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-10 19:41:39 +02:00
|
|
|
|
// register die nur einmal auf bank1 + 2 existieren
|
2017-05-11 11:41:36 +02:00
|
|
|
|
if (index == ADDR_PCL + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_STATUS + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_FSR + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_PCLATH + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_INTCON + 0x80) index -= 0x80;
|
2017-05-10 19:41:39 +02:00
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
if (index == ADDR_PCL) // PC direkt setzen
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
wert &= 0xFF; // Only Low 8 Bit
|
|
|
|
|
uint high = GetRegister(ADDR_PCLATH);
|
|
|
|
|
high &= 0x1F; // Only Bit <0,1,2,3,4>
|
|
|
|
|
high <<= 8;
|
|
|
|
|
|
|
|
|
|
PCCounter = (int) (high | wert) - 1;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
2017-05-11 11:41:36 +02:00
|
|
|
|
|
2017-05-11 11:47:53 +02:00
|
|
|
|
if (index == ADDR_INDF) // indirekte adresierung
|
|
|
|
|
{
|
|
|
|
|
if (Register[ADDR_FSR] % 0x80 != 0) SetRegister(Register[ADDR_FSR], wert);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
Register[index] = wert;
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
public uint GetRegisterOhneBank(uint index)
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
if (index == ADDR_UNIMPL_A) return 0;
|
|
|
|
|
if (index == ADDR_UNIMPL_B) return 0;
|
|
|
|
|
|
2017-05-10 19:41:39 +02:00
|
|
|
|
// register die nur einmal auf bank1 + 2 existieren
|
2017-05-11 11:41:36 +02:00
|
|
|
|
if (index == ADDR_PCL + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_STATUS + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_FSR + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_PCLATH + 0x80) index -= 0x80;
|
|
|
|
|
if (index == ADDR_INTCON + 0x80) index -= 0x80;
|
|
|
|
|
|
2017-05-11 11:47:53 +02:00
|
|
|
|
if (index == ADDR_INDF) // indirekte adresierung
|
|
|
|
|
{
|
|
|
|
|
if (Register[ADDR_FSR] % 0x80 != 0) return 0;
|
|
|
|
|
return GetRegister(Register[ADDR_FSR]);
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
return Register[index];
|
|
|
|
|
}
|
2017-05-10 19:41:39 +02:00
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
private uint GetRegister(uint index)
|
|
|
|
|
{
|
2017-05-10 12:00:41 +02:00
|
|
|
|
if ((Register[ADDR_STATUS] & STATUS_BIT_RP0) == STATUS_BIT_RP0)
|
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
return GetRegisterOhneBank(0x80 + index);
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
return GetRegisterOhneBank(index);
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
private void SetRegister(uint index, uint wert)
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
if ((Register[ADDR_STATUS] & STATUS_BIT_RP0) == STATUS_BIT_RP0)
|
|
|
|
|
{
|
|
|
|
|
SetRegisterOhneBank(0x80 + index, wert);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
SetRegisterOhneBank(index, wert);
|
|
|
|
|
}
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
|
|
|
|
|
2017-05-11 10:49:42 +02:00
|
|
|
|
public void SetRegisterOhneBank(uint index, uint bit, bool wert)
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
SetRegisterOhneBank(index, SetBit(GetRegisterOhneBank(index), bit, wert));
|
2017-05-10 12:00:41 +02:00
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}
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2017-05-11 11:31:25 +02:00
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|
2017-05-11 11:41:36 +02:00
|
|
|
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private void SetRegister(uint index, uint bit, bool wert)
|
2017-05-10 12:00:41 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
SetRegister(index, SetBit(GetRegister(index), bit, wert));
|
2017-05-10 12:00:41 +02:00
|
|
|
|
}
|
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|
|
|
|
2017-05-11 11:41:36 +02:00
|
|
|
|
public bool GetRegisterOhneBank(uint index, uint bit)
|
2017-05-10 16:30:58 +02:00
|
|
|
|
{
|
2017-05-11 11:41:36 +02:00
|
|
|
|
return GetBit(GetRegisterOhneBank(index), bit);
|
2017-05-10 16:30:58 +02:00
|
|
|
|
}
|
|
|
|
|
|
2017-05-10 12:00:41 +02:00
|
|
|
|
public static bool AdditionDigitCarry(uint a, uint b)
|
|
|
|
|
{
|
|
|
|
|
a &= 0x0F;
|
|
|
|
|
b &= 0x0F;
|
|
|
|
|
|
|
|
|
|
return (a + b) > 0x0F;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static bool SubtractionDigitCarry(uint a, uint b)
|
|
|
|
|
{
|
|
|
|
|
b = (~b) + 1;
|
|
|
|
|
|
|
|
|
|
return AdditionDigitCarry(a, b);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static bool GetBit(uint val, uint pos)
|
|
|
|
|
{
|
|
|
|
|
return (val & SHL(1, pos)) != 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static uint SHL(uint val, uint steps)
|
|
|
|
|
{
|
|
|
|
|
return (uint)((val) << ((int)steps));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static uint SHR(uint val, uint steps)
|
|
|
|
|
{
|
|
|
|
|
return (uint)((val) >> ((int)steps));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static uint SetBit(uint val, uint pos, bool bit)
|
|
|
|
|
{
|
|
|
|
|
return bit ? (val | SHL(1, pos)) : (val & ~SHL(1, pos));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
}
|