master
Mike Schwörer 5 years ago
parent e064604cf0
commit 9ddb13cb41
Signed by: Mikescher
GPG Key ID: D3C7172E0A70F8CF
  1. 4
      PIC_Simulator/Form1.cs
  2. 40
      PIC_Simulator/PIC/PICProgramm.cs
  3. 31
      TPicSim Testprogramme/TPicSim1X.LST
  4. 64
      TPicSim Testprogramme/TPicSim1X.src

@ -203,8 +203,8 @@ namespace PIC_Simulator
lvSpecial.Items[3].SubItems[1].Text = string.Format("0b{0}", Convert.ToString(programm.GetRegisterOhneBank(PICProgramm.ADDR_OPTION), 2).PadLeft(8, '0'));
lvSpecial.Items[4].SubItems[1].Text = string.Format("0b{0}", Convert.ToString(programm.GetRegisterOhneBank(PICProgramm.ADDR_INTCON), 2).PadLeft(8, '0'));
lvSpecial.Items[5].SubItems[1].Text = string.Format("{0}ms", programm.Stepcount * int.Parse(insertTime.Text));
lvSpecial.Items[6].SubItems[1].Text = "0b" + Convert.ToString(programm.Register[PICProgramm.ADDR_PORT_A], 2).PadLeft(8, '0');
lvSpecial.Items[7].SubItems[1].Text = "0b" + Convert.ToString(programm.Register[PICProgramm.ADDR_PORT_B], 2).PadLeft(8, '0');
lvSpecial.Items[6].SubItems[1].Text = "0b" + Convert.ToString(programm.Latch_RA, 2).PadLeft(8, '0');
lvSpecial.Items[7].SubItems[1].Text = "0b" + Convert.ToString(programm.Latch_RB, 2).PadLeft(8, '0');
lvSpecial.Items[8].SubItems[1].Text = programm.GetRegisterOhneBank(PICProgramm.ADDR_STATUS, PICProgramm.STATUS_BIT_C) ? "1" : "0";
lvSpecial.Items[9].SubItems[1].Text = programm.GetRegisterOhneBank(PICProgramm.ADDR_STATUS, PICProgramm.STATUS_BIT_DC) ? "1" : "0";
lvSpecial.Items[10].SubItems[1].Text = programm.GetRegisterOhneBank(PICProgramm.ADDR_STATUS, PICProgramm.STATUS_BIT_Z) ? "1" : "0";

@ -858,29 +858,53 @@ namespace PIC_Simulator.PIC
Zaehler.Reset();
}
Register[index] = (byte)(wert & 0xFF);
if (index == ADDR_PORT_A || index == ADDR_TRIS_A)
if (index == ADDR_PORT_A)
{
var ra = Register[ADDR_PORT_A];
var ta = Register[ADDR_TRIS_A];
Latch_RA = (byte)(wert & 0xFF);
for (uint i = 0; i < 8; i++)
{
if (!GetBit(ta, i)) Latch_RA = (byte)SetBit(Latch_RA, i, GetBit(ra, i));
if (!GetBit(ta, i)) Register[ADDR_PORT_A] = SetBit(Register[ADDR_PORT_A], i, GetBit(Latch_RA, i));
}
return;
}
if (index == ADDR_PORT_B || index == ADDR_TRIS_B)
if (index == ADDR_PORT_B)
{
var rb = Register[ADDR_PORT_B];
var tb = Register[ADDR_TRIS_B];
Latch_RB = (byte)(wert & 0xFF);
for (uint i = 0; i < 8; i++)
{
if (!GetBit(tb, i)) Latch_RB = (byte)SetBit(Latch_RB, i, GetBit(rb, i));
if (!GetBit(tb, i)) Register[ADDR_PORT_B] = SetBit(Register[ADDR_PORT_B], i, GetBit(Latch_RB, i));
}
return;
}
if (index == ADDR_TRIS_A)
{
var ta = (byte)(wert & 0xFF);
for (uint i = 0; i < 8; i++)
{
if (!GetBit(ta, i)) Register[ADDR_PORT_A] = SetBit(Register[ADDR_PORT_A], i, GetBit(Latch_RA, i));
}
}
if (index == ADDR_TRIS_B)
{
var tb = (byte)(wert & 0xFF);
for (uint i = 0; i < 8; i++)
{
if (!GetBit(tb, i)) Register[ADDR_PORT_B] = SetBit(Register[ADDR_PORT_B], i, GetBit(Latch_RB, i));
}
}
Register[index] = (byte)(wert & 0xFF);
}
private void Interrupt_RB(byte alt, byte neu)

@ -0,0 +1,31 @@
00001 ;TPicSim1
00002 ;Programm zum Test des 16F84-Simulators.
00003 ;Es werden alle Literal-Befehle gepr?ft
00004 ;(c) St. Lehmann
00005 ;Ersterstellung: 23.03.2016
00006 ;
00007
00008 ;Definition einiger Symbole
00009 ;zuerst Hardware-Register
00010 status equ 03h
00011 ra equ 05h
00012 rb equ 06h
00013
00014 ;f?r den Benutzer frei verwendbare Register
00015 count equ 0ch
00016
00017 ;Definition des Prozessors
00018 device 16F84
00019
00020 ;Festlegen des Codebeginns
00021 org 0
00022 start
0000 3011 00023 movlw 11h ;in W steht nun 11h, Statusreg. unver?n
0001 0085 00024 MOVWF 05h
00025
0002 3012 00026 movlw 12h ;in W steht nun 11h, Statusreg. unver?n
0003 0086 00027 MOVWF 06h
00028
00029 ende
0004 2804 00030 goto ende ;Endlosschleife, verhindert Nirwana
00031

@ -1,33 +1,31 @@
;TPicSim1
;Programm zum Test des 16F84-Simulators.
;Es werden alle Literal-Befehle gepr?ft
;(c) St. Lehmann
;Ersterstellung: 23.03.2016
;
;Definition einiger Symbole
;zuerst Hardware-Register
status equ 03h
ra equ 05h
rb equ 06h
;f?r den Benutzer frei verwendbare Register
count equ 0ch
;Definition des Prozessors
device 16F84
;Festlegen des Codebeginns
org 0
start
movlw 11h ;in W steht nun 11h, Statusreg. unver?ndert
andlw 30h ;W = 10h, C=x, DC=x, Z=0
iorlw 0Dh ;W = 1Dh, C=x, DC=x, Z=0
sublw 3Dh ;W = 20h, C=1, DC=1, Z=0
xorlw 20h ;W = 00h, C=1, DC=1, Z=1
addlw 25h ;W = 25h, C=0, DC=0, Z=0
ende
goto ende ;Endlosschleife, verhindert Nirwana
;TPicSim1
;Programm zum Test des 16F84-Simulators.
;Es werden alle Literal-Befehle gepr?ft
;(c) St. Lehmann
;Ersterstellung: 23.03.2016
;
;Definition einiger Symbole
;zuerst Hardware-Register
status equ 03h
ra equ 05h
rb equ 06h
;f?r den Benutzer frei verwendbare Register
count equ 0ch
;Definition des Prozessors
device 16F84
;Festlegen des Codebeginns
org 0
start
movlw 11h ;in W steht nun 11h, Statusreg. unver?ndert
MOVWF 05h
movlw 12h ;in W steht nun 11h, Statusreg. unver?ndert
MOVWF 06h
ende
goto ende ;Endlosschleife, verhindert Nirwana
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